1. Field of the Invention
The invention relates in general to a structure of nitride read-only memory (NROM) cells, and more particularly to the structure of discrete NROM cells fabricated according to the self-aligned process.
2. Description of the Related Art
The memory devices for non-volatile storage of information, such as read only memory (ROM), programmable read only memory (PROM), erasable programmable read only-memory (EPROM), and other advanced memory devices, are currently used in the worldwide industries. The other advanced memory devices that involve more complex processing and testing procedures include electrically erasable programmable read only memory (EEPROM), flash EEPROM, and nitride read-only memory (NROM). These advanced memory devices can accomplish the tasks that ROM can""t do. For example, using EEPROM devices in circuitry permits in-circuit erasing and reprogramming of the device.
The main characteristic of NROM is dual bit cells having multiple threshold voltage levels, where every two threshold voltage levels together store a different bit. Others store one bit on either side of the cell. The conventional structures and fabricating methods of NROM cell are described in a lot of articles and references.
FIG. 1 is a cross-sectional view of a conventional NROM cell. The substrate 10 is implanted with a source 12 and a drain 14. On the top of substrate 10 lies an ONO structure, having a nitride layer 17 between a top oxide layer 16 and a bottom oxide layer (tunneling oxide layer) 18. A number of BD (buried diffusion) oxides 20 are formed to isolate the adjacent ONO structure and form the channels 22. The conventional structure of the NROM cell which contains dual bits in one cell is also depicted in FIG. 1. The larger region (encircled with the dashed line) denotes a NROM cell 30, and the two smaller regions encircled with the dashed line denote the first bit 32 and the second bit 34.
In the NROM cell, the nitride layer 17 provides the charge retention mechanism for programming the memory cell. Under normal condition, the electrons are introduced into the nitride layer 17 during programming of the cell, while the holes are introduced into the nitride layer 17 to neutralize or combine the electrons during erasing of the cell. However, nitride tends to trap electrons that are introduced in the nitride layer 17 due to its property. If the electrons are trapped in the nitride layer 17, the cell is under programming.
Additionally, according to the hot electron injection phenomenon, some hot electrons will penetrate through the bottom oxide layer 18, especially when it is thin, and are then collected in the nitride layer 17. A concentrated charge caused by the hot electrons significantly raises the threshold voltage of the portion of the channel 22 under charge to be higher than the threshold voltage of the remaining portion of the channel 22. When the cell is programmed, the concentrated charge is presented and the raised threshold voltage does not permit the cell to go to the conductive state. In a normal state, which the concentrated charge is not presented, the reading voltage over the channel can overcome the threshold voltage of the channel 22 and consequently the channel 22 is conductive.
Moreover, the conventional NROM cell is generally fabricated by photolithography, and has drawbacks. For example, the implant and the bits are not easily formed at the right position and could be shifted, so that the efficiency of the NROM cell is decreased.
It is therefore an object of the invention to provide a structure of discrete NROM cell, so that the symmetrical positions of the source/drain implant and ONO structure can be precisely controlled.
The invention achieves the above-identified objects by providing a discrete NROM cell, comprising: a substrate; a first ON stacking gate and a second ON stacking gate over the substrate, wherein the ON stacking gate is a structure having a nitride layer over a bottom oxide layer; an oxide layer formed over the substrate and covering the first and second ON stacking gates; a polysilicon layer formed over the oxide layer; and the source/drain implanted in the substrate and next to the ON stacking gates.
Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.